Known Issue: v2.1, v1.3, v1.2, v1.1
Depending on the device targeted and mode of operation of the core, the external SPI flash storage device might need to be put in the 32-bit addressing mode due to the size of the data being stored.
The external shim interfacing with the SPI device does this by issuing the "enable 32-bit addressing" command 0xB7.
The external shim is in the provided example design directory in the file named sem_ext.v[hd].
The design begins to issue the command once GSR is released, however the controller resets the shim causing the command to get truncated and resent.
The only configurations impacted by this problem are the following Virtex-6 devices and operation modes:
If you are using any other configuration, this problem does not impact your design.
This is more of a cosmetic issue than a functional problem.
Issuing the command multiple times, even if it is truncated does not have any negative impact on the SPI flash device.
This issue is fixed in the v2.2 release which will be part of the 13.3 ISE software release.