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AR# 43107

7 Series Integrated Block Wrapper for PCI Express - Missing block RAM LOC constraints in UCF

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

The following core configurations do not produce the needed block RAM LOC constrains in the UCF file which result in timing problems:

  • x8 gen 1 and x4 gen 2 up to 256 byte MPS Good/High Performance and 512 byte MPS with Good Performance
  • x8 gen 2, x8 gen 1, and x4 gen 2with 512 byte MPS and High Performance

The "performance" setting of Good or High is selected on page 4 of the CORE Generator customization interface under theblock RAM configuration options.

MPS stands for the Maximum Payload Size. This is also selected on page 4 of the interface under Device Capabilities.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution

To obtain the correct block RAM constraints, you need to determine the base block RAM LOC constraint for the device and block in use. You can do this by generating a separate substitute core targeting the device and package in use. For the substitute core, target it as an x8 gen 2 with 256 MPS. After generating thesubstitute core, open the UCF file found in the example_design directory.

Since the block RAM locations vary depending on the device and the block being used, astarting point for the XY locations is needed. Use the LOC constraint for the block RAM instance "pcie_brams_tx/brams[1]".

For the combinations that require only 4 block RAM which isx8 gen 1 and x4 gen 2 up to 256 byte MPS Good/High Performance and 512 byte MPS with Good Performance, copy the constraints from the newly generatedsubstitutecore directly into the existing UCF. For reference, this configuration uses the following block RAM location numbering.X<a> is the starting X location value and Y<b> is the starting Y location value from the substitute x8 gen 2 core for the device and package in use.

x8 gen 1 and x4 gen 2 up to 256 byte MPS Good/High Performance and 512 byte MPS with Good Performance

pcie_brams_tx/brams[1].... X<a>Y<b>
pcie_brams_tx/brams[0] .... X<a>Y<b+1>
pcie_brams_rx/brams[1].... X<a>Y<b+3>
pcie_brams_rx/brams[0] .... X<a>Y<b+4>

For thex8 gen 2, x8 gen 1, and x4 gen 2 with 512 byte MPS and High Performancecores, they require 8 block RAM constraints which need to be created.

Using the constraint for the *pcie_brams_tx/brams[1] block RAM instance in the substitute core's UCF, applythe following algorithm to obtain the placement for the rest of the block RAM. Again, X<a> is the starting X location value and Y<b> is the starting Y location value from thesubstitute x8 gen 2 core for the device and package in use.

x8 gen 2, x8 gen 1 and x4 gen 2 with 512 byte MPS and High Performance

pcie_brams_tx/brams[3] .... X<a>Y<b>
pcie_brams_tx/brams[2] .... X<a>Y<b+1>
pcie_brams_tx/brams[1] .... X<a>Y<b+2>
pcie_brams_tx/brams[0] .... X<a>Y<b+3>
pcie_brams_rx/brams[3] .... X<a>Y<b+4>
pcie_brams_rx/brams[2] .... X<a>Y<b+5>
pcie_brams_rx/brams[1] .... X<a>Y<b+6>
pcie_brams_rx/brams[0] .... X<a+1>Y<b+5>

The above applies to all devices except for 485T when targeting Integrated Block X0Y0 and X0Y1. In those cases, uses the following.
Notice thepcie_brams_rx/brams[0] X constraint is minus 1 instead of plus 1:

pcie_brams_tx/brams[3] .... X<a>Y<b>
pcie_brams_tx/brams[2] .... X<a>Y<b+1>
pcie_brams_tx/brams[1] .... X<a>Y<b+2>
pcie_brams_tx/brams[0] .... X<a>Y<b+3>
pcie_brams_rx/brams[3] .... X<a>Y<b+4>
pcie_brams_rx/brams[2] .... X<a>Y<b+5>
pcie_brams_rx/brams[1] .... X<a>Y<b+6>
pcie_brams_rx/brams[0] .... X<a-1>Y<b+5>

Examples

Example 1: The block RAM constraints for an x8 gen 1 design using a 256-byte MPSwith integrated block X0Y0targeting a xc7k325t-fbg676FPGA.


  1. Generate an x8 gen 2 design with 256 MPS for the xc7k325t-fbg676 targeting block X0Y0.
  2. Open the UCF and copy the block RAM location constraints.
  3. Generate the x8 gen 1 core and paste the constraintscopied in step 2into the UCF.

Example 2: The block RAM constraints for an x8 gen 2 design using a 512 byte MPS with High Performance and integrated block X0Y0targeting a xc7k325t-fbg676 device. This configuration needs 8 block RAM.


  1. Generate an x8 gen 2 design with 256 MPS for the xc7k325t-fbg676 targetingintegrated block X0Y0.
  2. Open the UCF and find the block RAM location constraints. Note that the constraints have been shortened to make them easily readable, but the entire instance path must be used in the UCF file.
    INST ".../pcie_bram_top/pcie_brams_rx/brams[0].ram/..." LOC = RAMB36_X4Y34 ;
    INST ".../pcie_bram_top/pcie_brams_rx/brams[1].ram/..." LOC = RAMB36_X4Y33 ;
    INST ".../pcie_bram_top/pcie_brams_tx/brams[0].ram/..." LOC = RAMB36_X4Y31 ;
    INST ".../pcie_bram_top/pcie_brams_tx/brams[1].ram/..." LOC = RAMB36_X4Y30 ;
  3. Using the constraint forpcie_brams_tx/brams[1] as the base constraint, create the new constraints. The base constraint is used forpcie_brams_tx/brams[3] when 8 block RAM are needed. The constraints are then:
    INST ".../pcie_bram_top/pcie_brams_tx/brams[3].ram/..." LOC = RAMB36_X4Y30 ;
    INST ".../pcie_bram_top/pcie_brams_tx/brams[2].ram/..." LOC = RAMB36_X4Y31 ;
    INST ".../pcie_bram_top/pcie_brams_tx/brams[1].ram/..." LOC = RAMB36_X4Y32 ;
    INST ".../pcie_bram_top/pcie_brams_tx/brams[0].ram/..." LOC = RAMB36_X4Y33 ;
    INST ".../pcie_bram_top/pcie_brams_rx/brams[3].ram/..." LOC = RAMB36_X4Y34 ;
    INST ".../pcie_bram_top/pcie_brams_rx/brams[2].ram/..." LOC = RAMB36_X4Y35 ;
    INST ".../pcie_bram_top/pcie_brams_rx/brams[1].ram/..." LOC = RAMB36_X4Y36 ;
    INST ".../pcie_bram_top/pcie_brams_rx/brams[0].ram/..." LOC = RAMB36_X5Y35 ;

If you have any questions or problems following these steps, please open a WebCase with Xilinx Technical Support and reference (Xilinx Answer 43107). Also, include the XCO file for the core that you plan to use. The XCO file is created by the CORE Generator tool when the core is generated and is located in the project directory as <name of core>.xco.


Revision History

12/06/2011 - Added version resolved reference to AR 40469
07/14/2011 - Initial Release

Linked Answer Records

Master Answer Records

AR# 43107
Date Created 07/14/2011
Last Updated 05/20/2012
Status Active
Type Known Issues