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AR# 43175

ML50x - CPLD does not forward PERST# to FPGA

Description

The ML50x Evaluation Platform does not pass the PCI Express reset signal to the FPGA (PCIE_PERST_B).

The ML50x board receives the PCIe reset signal at the CPLD by means of the PCIe bus connection. By default, the CPLD functionality/program does not pass this along to the FPGA.

How can the PCIe reset signal be passed to the FPGA?

Solution

PERST# connectivity to the FPGA can be achieved by modifying the CPLD code. The ML50x CPLD source code is located at:
http://www.xilinx.com/products/boards/ml505/files/ml50x_cpld_design.zip

The net PCIE_PERST is not used in the CPLD design; there is nothing attached to pin 7 in the CPLD's design or UCF.

However, it would be possible to pass PCI_PERST_B (CPLD pin 7) through to net CPLD_IO_1 (CPLD pin 87); CPLD_IO_1 connects to the FPGA.
The CPLD HDL code would need to be modified to buffer the signal on pin 7 to pin 87.

For example:
PCIe finger -> PCIE_PERST_B -> CPLD (U3-7) input {buffered through CPLD} (U3-87) output -> CPLD_IO_1 to FPGA (U1-W10) input

This results in the net PCIE_PERST_B being connected to net CPLD_IO_1 on the FPGA pin W10.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42965 ML50x - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 43175
Date Created 07/20/2011
Last Updated 12/15/2012
Status Active
Type General Article
Boards & Kits
  • ML501
  • ML505
  • ML506
  • ML507