LogiCORE IP DisplayPort v2.3 - Why is the CORE_ID register different for the Source and Sink cores?

AR#	43176	Search For Another Answer
Topic	Multimedia Video Imaging
Last Updated	07/19/2011
Status	Active

Description

Why is the CORE_ID register different for the Source and Sink cores?

Solution

The CORE_ID register is not part of the DisplayPort Specification. This is a register used to identify the Xilinx Core Version. In the DisplayPort v2.3, the CORE_ID version is wrong and should be ignored.

This issue will be addressed in the next version of the DisplayPort IP.

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.