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AR# 43176

LogiCORE IP DisplayPort v2.3 - Why is the CORE_ID register different for the Source and Sink cores?

Description

Why is the CORE_ID register different for the Source and Sink cores?

Solution

The CORE_ID register is not part of the DisplayPort Specification. This is a register used to identify the Xilinx Core Version. In the DisplayPort v2.3, the CORE_ID version is wrong and should be ignored.

This issue will be addressed in the next version of the DisplayPort IP.

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 43176
Date Created 07/19/2011
Last Updated 05/23/2014
Status Archive
Type General Article
IP
  • DisplayPort