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AR# 43181

MIG Spartan-6 MCB - Simulation Parameters


This section of the MIG Design Assistant focuses on Simulation Parametersfor Spartan-6 MIG designs.

Note:This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG.Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


It is strongly recommended that you modify parameters via the MIG GUI. If a parameter is modified outside of MIG, it should be understood correctly. These parameters at the testbench impact the MIG core behavior. Use the following parameters to implement a Spartan-6 Memory Controller Block (MCB) simulation correctly:

  • C_MEMCLK_PERIOD - Memory frequency. Also defines the default clock input frequency.
  • C_CLKFBOUT_MULT - Multiplier of VCO of PLL.
  • C_DIVCLK_DIVIDE - Divider of VCO of PLL.
  • C_CLKOUT0_DIVIDE - Divider of CKLOUT0(clk_2x).
  • C_CLKOUT1_DIVIDE - Divider of CLKOUT1(clk_2x_180).
  • C_CLKOUT2_DIVIDE - Divider of CLKOUT2(user clock).
  • C_CLKOUT3_DIVIDE - Divider of CLKOUT3(calibration clock).
  • C_CALIB_SOFT_IP - Simulate or implement the design. "TRUE" is recommended in simulation to reduce simulation time.
  • C_RST_ACT_LOW - Active reset level ofc3_sys_rst_n. Default is low.

For other implementation parameters, please see theSpartan-6 FPGA Memory Controller User Guide(UG388).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37500 MIG Design Assistant - Spartan-6 Simulation N/A N/A
43162 MIG Spartan-6 MCB - User Design Simulation Debug N/A N/A
AR# 43181
Date Created 08/22/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • MIG