The system clock input must be in the same column as the memory interface, which should be allocated to either a Single Region Clock Capable (SRCC) I/O pair or a Multi-Region Clock Capable (MRCC) I/O pair. If this pin is connected in the same banks as the memory interface, the MIG tool selects an I/O standard compatible with the interface, such as DIFF_SSTL15 or SSTL15. If sys_clk is not connected in a memory interface bank, the MIG tool selects an appropriate standard such as LVCMOS18 or LVDS. The UCF can be modified as desired after memory controller generation.
For more information on clocking guidelines and the sharing ofsys_clk between controllers, please refer to theMIG 7 Series DDR3/DDR2 Clocking Guidelines(Xilinx Answer 40603).