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AR# 43190

MIG 7 Series 1.2 DDR3 - How long can DQS be delayed during write leveling?

Description

How long can DQS be delayed during write leveling? What is the total number of taps that can be used for write leveling?

Solution

During write leveling, PHASE_OUT uses fine delay and coarse delay to adjust the phase of DQS. Fine delay resolution is 1/64 ofdata period. When DDR3 runsabove 400 MHz, themaximum number of coarse taps is 4. Therefore, the total available delay tap is 64x4=256, which are 2 CK cycles. This means DQS can be delayed for 2 cycles total.

When DDR3 runs blow 400 MHz, the maximum number of coarse taps is 7. The total available delay tapis 64x7=448, which are 3.5 CK cycles.
AR# 43190
Date Created 07/21/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex
IP
  • MIG