After updating to the 13.2 release, my design fails to pass DRC during MAP.
The design could be implemented in previous versions.
The following error is reported:
Why is this happening?
Starting from build version O.61xd, the reference clock sourcing/forwarding rules for serial transceivers have been added to MAP DRC.
For example, in Virtex-6 architecture, the following rules declared in (UG366) are added to DRC:
1. The number of Quads above the sourcing Quad must not exceed one.
2. The number of Quads below the sourcing Quad must not exceed one.
3. The total number of Quads sourced by an external clock pin pair (MGTREFCLKN/MGTREFCLKP) must not exceed 3 Quads (or 12 GTX transceivers).
If any of above rules are violated, the error message is reported.
This error message is valid and the design must be changed to follow the rules.
Note: the design can still be implemented by disabling MAP DRC using the following environment variable regardless of the shrink of jitter margin.