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AR# 43194

13.2 BitGen - "ERROR:PhysDesignRules:2066 - Component xxx is configured for ISERDESE1"


The following DRC error is reported by BitGen:

"ERROR:PhysDesignRules:2066 - Component xxxxxx is
configured for ISERDESE1. A routethru from the /ILOGIC_XmYn/DDLY to
/ILOGIC_XmYn/O pins, configuring a second input path for the DDLY pin is in
conflict with ISERDESE1 configuration."

Howcan Iresolve this error?


Thiserror occursbecause the DDLY to O routethru in the ISERDESE1 component is used, butconflicts with the ISERDESE1 configuration.WhenISERDESE1is in use and the D pin is used for the sequential data input, the DDLY to O routethru is only available with IOBDELAY attribute of ISERDESE1 set to "BOTH".

To resolve this error, change the IOBDELAY attribute of ISERDESE1 to "BOTH".

Note: When the sequential data input goes into not only the D pin ofISERDESE1, but also other components such as output pads, slices, MMCM, and so on,the DDLY to O routethru will be used because of the routing resource limitation.

AR# 43194
Date 05/16/2012
Status Active
Type Error Message
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.1
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