GTX Transceiver Attribute Updates for Initial Engineering Sample (ES) Silicon

The next table shows the attribute updates that you must make to the GTX wrapper generated by the 7 series FPGA Transceiver Wizard to ensure reliable operation for the Initial ES silicon.

Note: The ISE Design Suite 13.3 generates these attribute updates natively when you use v1.5 of the 7 series FPGA Transceiver Wizard. However, for these attribute updates to be generated correctly, please make sure to select the correct part/package/speed grade combination to enable the Initial ES option under "Silicon Revision" on the Wizard GUI. The Initial ES support in this tool/wizard release is only for the following:

• Kintex-7 XC7K325T (ffg676 and ffg900 packages), Virtex-7 XC7VX485T (ffg1761 and ffg1927 packages)
• -1 and -2 speed grades

In ISE Design Suite 13.4, v1.5 of the 7 series FPGA Transceiver Wizard generates settings for only Initial ES silicon and v1.6 supports only the General ES silicon. The bit streams for Initial ES cannot be used on General ES silicon and vice versa. The updated v1.5 (v1.5 Rev 1) in ISE Design Suite 13.4 generates updated RXCDR_CFG values based on divider and PPM settings. The newer Wizard version v1.5 Rev2 in ISE 14.2/Vivado 2012.2 design tools alsosupports the Virtex-7 XC7V2000T Initial ES devices.

Notes:

1. For QPLL operating in 5.93 GHz to 6.6 GHz range (this is not the data rate but VCO frequency).
2. CPLL/QPLL Full-rate setting: For QPLL operation in 5.93 to 6.6 Gb/s line rate and CPLL operation in 3.2 to 6.6 Gb/s line rate with divider of 1.
3. CPLL/QPLL Half-rate setting: For QPLL operation in 2.965 to 3.3 Gb/s line rate and CPLL operation in 1.6 to 3.3 Gb/s line rate with divider of 2.
4. The port RXCDRLOCK is only a coarse indicator of CDR lock and this port is not supported. It is recommended to verify the incoming data.

TXOUTCLK and RXOUTCLK Ports Restrictions and Use Cases

There are some restrictions in using TXOUTCLK and RXOUTCLK for the Initial ES silicon. The following rules must be followed for proper operation of TXOUTCLK and RXOUTCLK:

• Use either TXOUTCLK or RXOUTCLK within any GTX channel, not both.
• Use either TXOUTCLK of GTX0 or RXOUTCLK of GTX1, not both.
• Use the reference clock directly from IBUFDS_GTXE2 to drive the fabric logic and GTX user clocks when necessary ([TX/RX]USRCLK, [TX/RX]USRCLK2).

RXOUTCLKSEL must be set to 3'b000 when RXOUTCLK is not used to output the clock and TXOUTCLKSEL must be set to 3'b000 when TXOUTCLK is not used to output the clock.

Use Cases

The following are some suggested use cases to implement designs to satisfy the above requirements:

TX Buffer Enabled Case

When TX buffer is used, use output of IBUFDS_GTE2 to route the GTX transceiver reference clock to fabric clocking resources.

RX Buffer Enabled Case

When RX elastic buffer is used, RXOUTCLKSEL of that lane must be set to 3'b000. If RX recovered clock must be routed out to the fabric, the clock routing should be planned carefully considering TXOUTCLK usage in mind.

Buffer Bypass Case

1. Consider enabling the TX and/or RX buffer for the Initial ES silicon.
2. For a TX buffer bypass, if there are unused transceivers, make use of the unused lane to route TXOUTCLK, and implement manual multi-lane alignment. For example, a single-lane TX buffer bypass in auto mode can turn into a 2-lane buffer bypass using manual multi-lane alignment. The unused lane will be used to route TXOUTCLK and perform alignment. The manual phase alignment steps are described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). In addition, a work-around is required to enable the manual alignment mode in the Initial ES silicon as described in (Xilinx Answer 43340). This work-around is not required if using the v1.5 of 7 series FPGA Transceiver Wizard in ISE Design Suite 13.3.
3. For an RX buffer bypass, consider using RX buffer bypass in multi-lane mode to minimize the number of RXOUTCLK required.
4. For applications needing both TX and RX buffer bypass (CPRI, OBSAI), place TX and RX on different lanes, and use single-lane auto mode for each direction.

QPLL Use Mode and Work-around

To ensure that the QPLL frequency band has optimal margin across Voltage and Temperature variations, the attached coarse calibration module "qpll_cal.v" must be incorporated in the user design. An example instantiation of this module is provided in the file "qpll_fix_top.v".

qpll_cal.v
qpll_fix_top.v

This module is included in the v1.5 of 7 Series FPGA Transceiver Wizard in ISE Design Suite 13.3.

Receiver Link Margin/Equalization Selection

The receiver can have a reduction in jitter tolerance when used in full-rate mode (RXOUT_DIV = 1). It is recommended where possible to always use data rates where RXOUT_DIV = 2, 4, 8. This applies to both CPLL and QPLL.

The7 Series GTX receiver has two different modes of adaptive equalization called Low-Power Mode (LPM) and Decision Feedback Equalization (DFE) mode. For more details, please refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). TheGTX receiver can support a channel with 12 dB loss at 6.6 Gb/s in both LPM and DFE modes. This is assuming PRBS31 data pattern and a TX launch amplitude of 850 mV Vp-p, diff, TX pre-cursor emphasis of around 2 dB and TX post-cursor emphasis of around 4 dB.

GTX Software Use Model Changes

For software use model changes and requirements for 7 series GTX transceivers, refer to (Xilinx Answer 43339).

Revision History

09/06/2012 - Fixed minor typos and corrections.
01/12/2012 - Updated RXCDR_CFG settings for different PPM scenarios.
12/12/2011 - Updated the table with a note on RXCDRLOCK port.
11/09/2011 - Added a note on supported Initial ES device combinations in v1.5 of the Wizard in ISE 13.3.
10/27/2011 - Added Wizard/ISE version information that includes the fixes.
10/17/2011 - Updated RXCDR_CFG to include values for both full-rate and half-rate.
08/25/2011 - Updated title to include Virtex-7 FPGA. Updated the table with BIAS_CFG setting for Virtex-7 FPGA.
08/16/2011 - Minor edits.
07/28/2011 - Initial release.