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AR# 43250 MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF Constraint is not Applied Across All Memory Banks

Description

When I generate a MIG design that spans multiple banks, I only see internal VREFused for the bank selected for address and control. Why does this occur if the other banks have inputs that need internal VREF?

Solution

This is incorrect behavior as internal VREF should be applied to all banks that require VREF. To work around the problem, add the INTERNAL_VREF constraint into the generated UCF for the missing banks.

Example 1: INTERNAL_VREF for Bank 14 using HSTL_II (1.5V), which requires a 0.75V reference voltage, uses the following constraint:

CONFIG INTERNAL_VREF_BANK14 = 0.75;

This is scheduled to be fixed in the 13.3 release.

For Internal/External VREF Guidelines, see (Xilinx Answer 42036).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42036 MIG 7 Series - Internal/External VREF Guidelines N/A N/A
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

Actions

AR# 43250
Date Created 07/28/2011
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
IP
  • MIG
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