Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
TheAXI EP Bridge v1.00a for PCI Express allows you to specify the AXI data width during customization of the bridge. The data sheet specifies the data width as a fixed value depending on the targeted device.
Will changing the data width affect the design?
NOTE: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
For the core to work properly, the AXI data width needs to be 64-bit for Virtex-6 FPGA and 32-bit for Spartan-6 FPGA. Otherwise, the TLPs will not transfer between the underlying Integrated Block for PCI Express and the enhanced interface within the AXI Bridge for PCI Express.In 13.3, there is a DRC indicating the appropriate data width for a targeted device.
11/21/2011 - Updated for 13.3
08/19/2011 - Initial Release