This section of the MIG Design Assistant focuses on synthesis and implementation debugging for Spartan-6 designs.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The following figure shows the flow for Spartan-6 MIG core synthesis and implementation.
Verify Successful Synthesis and Implementation
After theMIG core is generated, you can find a constraint file and script to run synthesis and implementation in the example_design/par or user_design/par directory. The script file name is "ise_flow.bat". This script includes all of the commands and parameters to run XST (or Synplify_Pro), Ngdbuild, Map, Par, Trce, and BitGen. If no error is reported during execution of these commands, there are no issues with the software environment.
Verify Modifications to the MIG Output
The MIG tool generates an MCB wrapper file. Modification is not supported for this module. If modification is required anyway, please verify itindependently in behavioral simulation, synthesis, and implementation. Also, memory-related, dual-purpose pins in the UCF cannot be modified because the Spartan-6 uses a hard memory controller and these pins are locked for memory purposesif the MCB is used.
Identify and Analyze Timing Failures
Timing constraints are generated for the MIG core and it is very important to check if timing meets the requirement. Please check the TRCE report (.twr or .twx) for any timing violations. If any violations exist, please ensure that the XST, MAP, andPAR command optionsare the same as defined in ise_flow.bat. If thereare stilltiming failures, please consider using PlanAhead to meet timing closure.
If all above steps do not help you, please open a WebCase.