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AR# 43294

13.2 EDK, AXI Ethernet v3.00.a - MDIO Transaction Errors at Link Speeds 10 Mbps with the Virtex-6 Hard TEMAC


When the AXI Ethernet is configured for MII, GMII, or RGMII (C_PHY_TYPE = 0, 1, or 3) operation with the Hard TEMAC (C_TYPE = 2) operating at 10 Mbps, MDIO transaction errors can occur.


To prevent errors from occurring, please configure the MDC clock frequency to be less than * MII_TX_CLK. Recall that the MDC frequency is adjusted by using the following equation:

fMDC = fHOSTCLK/((1 + Clock_Divide[5:0]) *2)

Because the HOSTCLK is driven by S_AXI_ACLK, if S_AXI_ACLK = 100 MHz, it is recommended that a value of at least 6?b101001 (41d) is used. This results in a MDC clock frequency that is 1.19 MHz or less. Even though a Clock_Divide setting of 6b'101000 (40d) seems like viable option, it is recommended to use a larger Clock_Divide setting. The larger setting reduces the MDC frequency and improves sampling accuracy.

Any time a reset or initialization is performed, the current software driver sets Clock_Divide to a default value of 6'b011101 (29d). You can change the Clock_Divide setting by either using the API or by writing to the lower six bits of the MII Management (MDIO) Configuration (MC) Register at offset 0x0000_0500. Perform the following steps when using the API to set Clock_Divide:

XAxiEthernet Mac;
XAxiEthernet_PhySetMdioDivisor(&Mac, 41);

Note: It is assumed that before calling "XAxiEthernet_PhySetMdioDivisor" you have already initialized the AxiEthernet hardware by calling the appropriate driver APIs (XAxiEthernet_CfgInitialize).
AR# 43294
Date Created 07/25/2011
Last Updated 10/05/2011
Status Active
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 SXT
  • AXI Ethernet