Why does a symmetrical interpolation filter use more DSP slices when the coefficients are >=18 bits in Spartan-6?
The FIR Compiler v5.0 or v6.2 appears to use too many DSP48 slices when creating a Symmetrical FIR with a coefficient width of 18.
For small FIRs, the expected utilization would be two DSP48 slices: one for the filtering and a second DSP48 slice to accumulate the symmetrical pairs.
More than two DSP48 slices are used when the coefficient bit width is >=18 bits because bit growth is occurring on the coefficients.
This is due to the symmetric pairs method used to support symmetrical coefficients for interpolating filters.
The poly-phase sub-filters are non-symmetric, but by combining pairs of them symmetry is regained.
This combination generates a bit of growth.
So, when the coefficients width is 18-bits, the growth to 19-bits pushes it over a single DSP48 on the Spartan-6 and generates an extended multiplier implementation.
There are a few ways to work around this issue:
1. Use a coefficient bit width of less than 18 bits.
2. In cases where the clock is fast enough, it might use fewer DSP slices, if the coefficient type is set to "non-symmetrical."
It can reduce the number of DSP slices to one as it does not require the second one for accumulating the symmetrical pairs.
Please see (Xilinx Answer 29138) for a detailed list of LogiCORE IP FIR Compiler Release Notes and Known Issues.