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AR# 43313 AXI Bridge for PCI Express - m_axi_arlock and m_axi_arcache are connected to the AXI write address channel

Description


Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

The AXI Bridge v1.00a for PCI Express incorrectly connects the m_axi_arlock and m_axi_arcache signals to AWLOCK and AWCACHE.

NOTE: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution


The root of this known issue is caused from typo in the axi_pcie_v2_1_0.mpd located in the following directory:

$XILINX_EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_00_a/data/

On line 213 and 214 of axi_pcie_v2_1_0.mpd, the incorrect assignment should be changed from:
PORT m_axi_arlock = AWLOCK, DIR = O, BUS = M_AXI
PORT m_axi_arcache = AWCACHE, DIR = O, VEC = [3:0], BUS = M_AXI, ENDIAN = LITTLE

to:
PORT m_axi_arlock = ARLOCK, DIR = O, BUS = M_AXI
PORT m_axi_arcache = ARCACHE, DIR = O, VEC = [3:0], BUS = M_AXI, ENDIAN = LITTLE

Revision History
11/21/2011 - Initial Release

Actions

AR# 43313
Date Created 11/22/2011
Last Updated 11/22/2011
Status Active
Type
IP
  • AXI PCI Express (PCIe)
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