This section of the MIG Design Assistant focuses onpin-out requirements for Spartan-6 MCB designs.This Answer Record points to additional information on verifying any placement changes, as well as detailed information on design requirements that cause common questions.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The MIG tool generates all necessary signals to communicate between the memory device and the MCB. Pin locations for all of these signals are pre-defined inSpartan-6 FPGA Packaging and Pinouts Product Specification (UG385).The first step in debugging issues encountered in hardware testing is to verify that the pin-out requirements of the Spartan-6 MCB design have been followed. You can find these guidelines in the Memory Device Interface section within the Spartan-6 FPGA Memory Controller User Guide (UG388).
In addition, the soft calibration module generated by the MIG toolrequires allocation of an additional pin (RZQ) for all MCB designs. RZQ is a required pin, but its location can be moved within the MCB bank. When Calibrated Input Termination is selected in the MIG tool, a ZIO pin is also generated for use with the soft calibration module. The ZIO location can also be moved but must placed on a bonded I/O within the MCB bank.
Please refer to following links for related information.
(Xilinx Answer 34934) -Is it possible to share PLL and BUFPLL_MCB resources in multi-controller designs?
(Xilinx Answer 36431) -Is there a preferred or required PLL location that should be used within the design?
(Xilinx Answer 34153) -Can MCB pins be swapped to help facilitate board layout?
(Xilinx answer 34055)- What are the requirements for the RZQ and XIO pins?