Please download the Virtex-5 Embedded TEMAC Wrapper - Debugging and Packet Analysis Guide.
Xilinx provides the Embedded Hard TEMAC solution on Virtex-4, Virtex-5, and Virtex-6 devices. You can generate the core with the CORE Generator software.The core comes with an example design that has an address swap module as client logic. The example swaps the source and destination address of the incoming MAC frame and transmits it back to the source.
The document attached with this answer record describes how to use ChipScope Pro to debug issues with the LogiCORE IP Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper. The document goes through a complete packet analysis in the generated example design to helpyou track the path of a particular packet starting from a host PC going through the core and the client logic, and then back to the host PC. Different interfaces in the design are identified for you to track the path of the frame and figure out where the issue resides. This will help youto focus your debugging efforts on a particular portion of the design.
To make it easier for new users of the core, the attached document describes all the steps required for generating the core and the modification required to implement the core on a Xilinx ML505 demo board.
08/16/2011 - Initial Release