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AR# 43338: Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII Operation at 10 Mbps, MDIO Transaction Errors Can Occur
Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII Operation at 10 Mbps, MDIO Transaction Errors Can Occur
When the Virtex-4, Virtex-5, or Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC is configured for MII, GMII, or RGMII operation at 10 Mbps, MDIO transactions errors can occur. This issue is not present when operating at speeds other than 10 Mbps.
To prevent MDIO transaction errors from occurring, configure the MDC clock frequency to be less than 1/2 the frequency of MII_TX_CLK. Lower MDC clock frequencies improve sampling accuracy and a frequency of less that 1.2 Mhz is recommended in this case to account for clock tolerances.
As described in the respective Embedded Tri-Mode Ethernet MAC user guide, recall that:
fMDC = fHOSTCLK/((1 + CLOCK_DIVIDE[5:0]) * 2).
So, for example, if HOSTCLK is 100 MHz, it is recommended that a divider of at least 6'b101001 (41d) is used. This will result in a MDC clock frequency that is 1.19 MHz or less. Even though a CLOCK_DIVIDE setting of 6'b101000 (40d) seems like viable option, it is recommended to use a larger CLOCK_DIVIDE setting. The larger setting will reduce the MDC frequency and improve sampling accuracy.
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