GTXE2_COMMON Use Model Change
BIAS_CFG is an attribute of the GTXE2_COMMON module and the correct settings are documented in (Xilinx Answer 43244) for the Initial ES silicon and (Xilinx Answer 45360) for the General ES silicon. However, for the correct BIAS_CFG to propagate through, the following use mode must be followed.
Otherwise, BIAS_CFG will be set incorrectly in the software model to 64'h0000000000000000.
To use the correct BIAS_CFG value, perform the following steps:
NOTE: After setting BIAS_CFG as above, the minimum connections required so that the tools do not optimize the GTXE2_COMMON block away are as follows:
1. GTXE2_COMMON port GTREFCLK0 should be connected to the incoming reference clock.
2. GTXE2_COMMON port QPLLOUTCLK should be connected to GTXE2_CHANNEL port QPLLCLK (all the used channels on the quad).
3. GTXE2_COMMON port QPLLREFCLKSEL should be 3'b001.
The GTXE2_COMMON instantiations should be performed in the gtwizard_v2_1.v file for Verilog, or gtwizard_v2_1.vhd for VHDL (gtwizard_v2_1 is the default name that will be replaced with the name that the user gives to the design on page 1 of the wizard). The GTXE2_COMMON instantiation can be obtained from a wizard example design that uses QPLL (example "gt_wizard_v2_2.v" and "gt_wizard_v2_2.vhd" files are attached where two GTXE2_COMMON's are instantiated).
This applies to (and the work-around is required for) all 7 series FPGA GTX silicon versions - Initial ES, General ES, Production silicon. The GTXE2_COMMON module is automatically instantiated when using the 7 series FPGA Transceiver Wizard v2.2 or later in ISE 14.2/Vivado 2012.2 tools or later for General ES or Production silicon. There have been instances in later software where the GTXE2_COMMON block is not placed correctly so that the BIAS_CFG will not be set correctly. In this case the software does issue a critical warning. See (Xilinx Answer 60638) for further explanation. For Initial ES silicon, v1.5 Rev 2 automatically instantiates the GTXE2_COMMON. When using other tool/wizard versions, the GTXE2_COMMON must be instantiated as described above.
IBUFDS_GTE2 Use Model Change
An IBUFDS_GTE2 primitive drives the GTX reference clocks and there are two IBUFDS_GTE2 elements per Quad as shown in Figure 2-4 of the 7 Series FPGAs GTX Transceivers User Guide (UG476), driving GTREFCLK0 and GTREFCLK1. The common use mode is to instantiate one IBUFDS_GTE2 and drive one of the two reference clocks. There is an issue in ISE 13.3 or earlier design tool models that causes the signal swing of the reference clock going into the Quad to be set incorrectly when only one IBUFDS_GTE2 primitive is instantiated in a Quad.
If only one IBUFDS_GTE2 primitive is instantiated to drive GTREFCLK0 or GTREFCLK1, then a second IBUFDS_GTE2 primitive must also be instantiated in the Quad to drive the other GTREFCLK.
The output of each IBUFDS_GTE2 must be connected to the correct GTREFCLK0 or GTREFCLK1 to prevent ISE tools from removing the primitive. It is okay to physically not drive a clock to the second IBUFDS_GTE2 that is instantiated.
Only the Quad with a reference clock physically coming in needs to have both the IBUFDS_GTE2 instantiated and this work-around is not necessary for the Quads that are just forwarding the reference clock from another Quad.
NOTE: The GTX Wizard takes advantage of the intelligent pin selection algorithm and always connects the clock input to GTREFCLK0, even though the default GUI selection in the CORE Generator tool is GTREFCLK1. When adding a second clock source, the intelligent pin selection algorithm will not swap the clock sources. You must check that the clock source is connected to the correct clock input, otherwise a MAP error occurs. When implementing the above work-around, multiple reference clock sources are connected to the GTX. Thus, the CPLLREFCLKSEL or QPLLREFCLKSEL ports are required to be selected correctly to choose between GTREFCLK0/1, GTNORTHREFCLK0/1, GTSOUTHREFCLK0/1. For more information, please refer to the 7 Series FPGAs GTX Transceivers User Guide (UG476).
This issue is fixed in ISE Design Suite 13.4 and the work-around is not required when using ISE 13.4 or newer tools.
IBUFDS_GTE2 Issue: Incorrect CLKSWING_CFG Attribute Setting in VHDL designs
In ISE 13.4 and earlier tool versions, the default value of the CLKSWING_CFG attribute in the IBUFDS_GTE2 primitive is set incorrectly for VHDL designs. This does not impact designs using Verilog; this only impacts VHDL designs that do not explicitly call out and set the CLKSWING_CFG attribute. This incorrect CLKSWING_CFG setting might result in transceiver performance degradation.
For VHDL designs, users must explicitly call out and set the CLKSWING_CFG to the correct value of 2'b11 in the IBUFDS_GTE2 instantiation. This software issue is fixed in ISE Design Suite 14.1.
Logic Simulation Issue with RX in LPM/DFE Modes
The software model in ISE Design Suite 13.3 will not simulate correctly when the receiver is in certain modes: in LPM mode (RXLPMEN=1'b1) and with the updated DFE related attributes as in (Xilinx Answer 43244) when in DFE mode (RXLPMEN=1'b0). This simulation model issue results in RXDATA being stuck at 0xFEFE.
To work around this issue, use DFE mode (RXLPMEN=1'b0) in logic (digital) simulation, but with the original software default settings (without updating the DFE-related attribute settings described above).
This issue is fixed in ISE Design Suite 13.4.
LPM Mode Selection Issue in the Wizard
When LPM mode is selected (RX equalization is set to "LPM-Auto" in page 3 of the GUI) in the 7 Series FPGA Transceivers Wizard, the port RXLPMEN is not set correctly to 1'b1.
In "[component_name]_gt.v or vhd" file, set RXLPMEN to 1'b1. This issue is fixed in v1.6 of the 7 Series FPGA Transceivers Wizard in ISE Design Suite 13.4.