When a multi-lane application requires a TX/RX buffer bypass, you must use a manual phase alignment. The steps for the manual phase alignment are available in the
7 Series FPGAs GTX Transceivers User Guide (UG476).
In addition, you must use the workaround below to enable the manual alignment mode in the Kintex-7 GTX Initial ES silicon. You do not need to perform this workaround if you are using the v1.5 of the 7 Series FPGAs Transceiver Wizard in ISE Design Suite 13.3.
TX:PCS_RSVD_ATTR[1] (Reg 0x06F[1]) needs to toggle from 0 to 1 after completion of GTTXRESET, and before the manual alignment procedure, that is, TXRESETDONE going high in response to GTTXRESET being asserted.
RX:PCS_RSVD_ATTR[2] (Reg 0x06F[2]) needs to toggle from 0 to 1 after completion of GTRXRESET, and before the manual alignment procedure, that is, RXRESETDONE going high in response to GTRXRESET being asserted.
NOTE: These bits need to toggle from 0 to 1, so you cannot statically set them in the UCF for the Initial ES silicon.