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AR# 43340

Kintex-7 GTX Transceiver - Buffer Bypass Manual Mode Enable Workaround for Initial Engineering Sample (ES) Silicon

Description

This answer record contains information on the manual phase alignment of Kintex-7 GTX transceivers in a multi-lane application that requires a TX/RX buffer bypass and a related workaround to enable the manual alignment mode for Kintex-7 GTX Initial ES silicon.

Solution

When a multi-lane application requires a TX/RX buffer bypass, you must use a manual phase alignment. 

The steps for the manual phase alignment are available in (UG476) 7 Series FPGAs GTX Transceivers User Guide.

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

In addition, you must use the workaround below to enable the manual alignment mode in the Kintex-7 GTX Initial ES silicon. 

Note: You do not need to perform this work-around if you are using v1.5 of the 7 Series FPGAs Transceiver Wizard in ISE Design Suite 13.3.

 

TX:
PCS_RSVD_ATTR[1] (Reg 0x06F[1]) needs to toggle from 0 to 1 after completion of GTTXRESET, and before the manual alignment procedure.

In other words, TXRESETDONE is going high in response to GTTXRESET being asserted.   


RX:
PCS_RSVD_ATTR[2] (Reg 0x06F[2]) needs to toggle from 0 to 1 after completion of GTRXRESET, and before the manual alignment procedure.

In other worlds, RXRESETDONE is going high in response to GTRXRESET being asserted.

 

NOTE: These bits need to toggle from 0 to 1, so you cannot statically set them in the UCF for the Initial ES silicon.

Linked Answer Records

Associated Answer Records

AR# 43340
Date Created 07/27/2011
Last Updated 05/11/2015
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7