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AR# 43347

Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record


This answer record highlights important requirements and known issues for the Kintex-7 FPGA Initial Engineering Sample (ES) program related to software and IP.These items are specifically relevant to designs targeting the Kintex-7 325T and 480T Initial ES FPGA devices (CES 9937). Additional silicon limitations might exist, so please reference the 7 Series Errata found on xilinx.com.

This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.


Kintex-7 Initial ES FPGA can be used with ISE 13.4 design tools. The ISE 13.4 tools include some software and IP fixes, however, it is primarily targeted for General ES devices, so some additional settings are required. Follow the steps listed below for your ISE tools version in the Software Requirements and IP Known Issues to start a design.

Software Requirements

  • ISE Design Suite 13.4 is available on the Xilinx Download Center.
  • Patches; this is the complete list of available patches for ISE 13.4 design tools targeting the Kintex-7 FPGA Initial ES silicon.
    • Required patches for all users:
      • (Xilinx Answer 43060) - Any user creating a bitstream for the Kintex-7 325T Initial ES device must install this BitGen patch.
    • Patches required based on usage:

Software Known Issues

IP Requirements

All 7 Series IP Cores are listed as Pre-Production in the CORE Generator "Status" field. Support of Pre-Production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, whichis ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records below for the most recent information. The list below includes all Pre-Production IP cores that have been hardware validated on Initial ES at this time:

  • 7 Series Integrated Block for PCI Express
  • Serial RapidIO Gen2 (v1.3) at 1.25 Gb/s, 2.5 Gb/s, and 3.125 Gb/s line rates

This list will be updated as hardware validation is completed. If there are further questions about hardware validation for a particular IP core, please contact a Field Application Engineer.

IP Known Issues for ISE Design Suite 13.4

  • 7 Series Integrated Block for PCI Express
    • All users of the Integrated Block for PCIe must update to ISE Design Suite 13.4 and use core version v1.3
    • (Xilinx Answer 40469) 7 Series Integrated Block Wrapper for PCI Express - Release Notes and Known Issues
    • (Xilinx Answer 43243) Virtex-7, Kintex-7 FPGA XC7K325T CES9937 Integrated Block for PCI Express - Active State Power Management Not Supported for Gen 2 Rates
    • The v1.3 core gives users an option of selecting between Initial ES (ES) and General ES (GES) silicon. When generating the core, there is a drop-downon panel 12 (last panel) ofthe customization GUI to select either "General ES" or "Initial ES" silicon. The same bitstream cannot be used in both IES and GES devices.
  • LogiCORE IP AXI EP Bridge for PCI Express (EDK)
    • All users of theLogiCORE IP AXI EP Bridge for PCI Express available in EDK must update to ISE Design Suite 13.4 and use core version v1.02a
    • (Xilinx Answer 44969)AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions
    • MIG 7 Series users need to use MIG 7 Series v1.4 available with ISE Design Suite 13.4 or later due to updated calibration changes and CKE/ODT implementation changes as outlined in (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
    • (Xilinx Answer 45195)MIG 7 Series v1.4 - Release Notes and Known Issues for all releases
    • (Xilinx Answer 43372) MIG 7 Series v1.2-v1.4 DDR3 - DQS Preamble is Not Always Detected Correctly for XC7K325T Initial Engineering Sample

Other Important Items

  • (Xilinx Answer 43244) Kintex-7, Virtex-7 GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial ES Silicon

Bitstream Compatibility Between Initial ESvs. General ES Silicon

The Initial ES bitstream cannot be used with General ES silicon and vice versa.

Revision History
09/24/12 - Minor update; no change to content
02/27/12 - Updated software requirement due to MIG known issues
01/18/12 - Updated for ISE 13.4 release
10/26/11 - Updated for ISE 13.3 release
09/29/11 - Consolidated all patches in one list in Software section
09/07/11 - Added 43949 for PCIe.
08/22/11 - Added QDRII+ and RLDRAMII to list of MIG validated IP
08/02/11 - Formatting updates
07/29/11 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51993 Xilinx 7 Series FPGA Solution Center - Top Issues N/A N/A

Child Answer Records

Associated Answer Records

AR# 43347
Date Created 07/28/2011
Last Updated 10/15/2012
Status Active
Type Known Issues
  • Kintex-7
  • ISE Design Suite - 13.4