This part of the MIG Design Assistant guidesyou to information on masking data with the user interface.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The write data mask inputs (pX_wr_mask) to the user interface can be used to offset the starting address byte location.
For example, to begin writing at byte address 0x01 when using a 32-bit (4-byte) user interface, the byte address presented to the command port of the user interface should be 0x00, but the least significant mask bit should be set to 1 such that only bytes at address 0x01 and higher are actually written.
For timing diagrams and more information, see the Spartan-6 FPGA Memory Controller User Guide(UG388); under "MCB Operation" -> "Addressing":
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43323 | MIG Spartan-6 MCB - Driving the User Interface | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 44094 | MIG Spartan-6 FPGA DDR2/DDR3 - How do I drive the user interface? | N/A | N/A |
| 43595 | MIG Spartan-6 FPGA DDR2/DDR3 - Using CORE Generator | N/A | N/A |
| 43323 | MIG Spartan-6 MCB - Driving the User Interface | N/A | N/A |