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AR# 4345

FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted

Description

Keyword: gsr, set flip-flop, verilog

Urgency: standard

Description: Example of a behavioral description of a preset and
reset FF upon power-up using FPGA Compiler as the synthesis tool.
This example is also incorperating a STARTUP block so that the
global set/reset signal is brought out to a user pin.

Solution

1

Connect the STARTUP block to a port as well as to every FF in the design.
By connecting the same port to all FF re/presets, the RTL testbench can match
the Timing testbench in terms of the global reset.
Map will issue the following expected warning:

WARNING:baste:22 - The signal "n110" is connected to the GR/GSR (global set/reset) pin on the STARTUP component as well as every asynchronous flip-flop set/reset in the design. Removing this signal from every flip-flop in the design (leaving the STARTUP connection) will reduce the amount of routing resources required to implement the design.

This is OK since we want that signal to be removed. Make sure to connect this signal to every inferred FF and Latch in the design or else the signal will not get removed and redundant routing will result.

2


module s_n_r_ffs (global_reset, CLK, DATA_RESET, DATA_PRESET, Q_RESET, Q_PRESET);

input global_reset, CLK, DATA_RESET, DATA_PRESET;
output Q_RESET, Q_PRESET;

reg Q_RESET, Q_PRESET;

STARTUP the_reset (.GSR(global_reset));

always @ (posedge CLK or posedge global_reset)
begin: RESET_FF
if (global_reset)
Q_RESET <= 1'b0;
else
Q_RESET <= DATA_RESET;
end

always @ (posedge CLK or posedge global_reset)
begin: PRESET_FF
if (global_reset)
Q_PRESET <= 1'b1;
else
Q_PRESET <= DATA_PRESET;
end

endmodule
AR# 4345
Date Created 07/28/1998
Last Updated 04/25/2007
Status Archive
Type General Article