UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43465

13.2 EDK, BSB - Why is the DDR3 DQ width set to 8 bits with my ML605 BSB generated project?

Description

Why is the DQ set to 8 bits with my ML605 Base System Builder (BSB) generated project when the ML605 supports 64-bits?

Solution

By defaultBSB is set forarea optimization, which uses only 8-DQ bits to save resources. Because MIG uses a /4 controller architecture to support high SDRAM speeds, a 64-bit wide interface would result in a 256-bit wide AXI interface andAXI Interconnect datapaths, consuming logic resources.

For64-bit DDR3 DQ width, switch the BSB choice from 'Area' to 'Performance'.

AR# 43465
Date Created 08/04/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 13.2
Boards & Kits
  • Virtex-6 FPGA ML605 Evaluation Kit