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AR# 43482

7 Series Transceivers - Reset Requirements Upon Configuration

Description

In the 7 series FPGAs GTX/GTH/GTP Transceivers, GTTXRESET and GTRXRESET need to default to Low upon configuration, and to be set to High some time after the configuration is done.

Solution

Upon configuration, you must initiate the GTTXRESET and GTRXRESET in sequential mode; that is, RESETOVRD=1'b0 and GTRESETSEL=1'b0.

If RESETOVRD and GTRESETSEL are already defaulted to the above values, then the GT resets: GTTXRESET and GTRXRESET cannot be asserted until a minimum of 500 ns after the configuration is complete. To keep the timing aligned with Figure 2-12 in the 7 Series FPGAs GTS Transceivers User Guide, it might be best to delay the CPLLRESET and the QPLLRESET as well.



If RESETOVRD and GTXRESETSEL are NOT defaulted to the above values, then you must do the following:
  1. Wait a minimum of 500 ns after GSR deassert.
  2. Set RESETOVRD and GTRESETSEL to 0.
  3. Wait another 300-500 ns.
  4. Assert resets.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 43482
Date Created 09/01/2011
Last Updated 01/16/2013
Status Active
Type General Article
Devices
  • Virtex-7
  • Kintex-7
  • Artix-7