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AR# 43488

EDK, xps_central_dma v2.03.a - DMA Busy (DMABSY) Incorrectly Deasserts During a DMA Transfer


During a DMA transfer, the DMA Busy (DMABSY) bit of the DMA Status Register (DMASR) can sometimes be '0' only for one clock.

If you use this status bit to detect the completion of DMA transfer, it can cause a mis-detection.


There are two workarounds:

  1. This issue can occur when the length (LENGTH) setting is 1, 2, 3, or 4.
    Set the length to larger than 5.
  2. Use the DMA Done (DD) interrupt to detect the completion of DMA transfer. 

A patch is available for xps_central_dma v2.03.a. 

Download and install the following patch to solve this issue:


This is currently not planned to be fixed in the the xps_central_dma core.

AR# 43488
Date 10/02/2014
Status Active
Type General Article
  • XPS Central DMA
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