The Virtex-6 DDR2/DDR3 MIG design has two clock inputs: the reference clock and the system clock input.
The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks (used in the user interface, controller, and PHY layers) and drives the MMCM instantiated in the infrastructure module.
The reference clock can be generated from the existing MMCM resource instead of driving it from an external clock source.
Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
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// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi or (not pll_lock);
(1) Input clock frequency is the same as memory controller frequency for all Virtex-6 designs.
So when clocking wizard is invoked, reference clock frequency of 200 MHz or 300 MHz might not be generated for various input frequencies.