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AR# 43581

Virtex-6 Integrated Block for PCI Express - Updated GTX Attributes for v1.7 Core Version

Description

When using the v1.7 Integrated Block Wrapper for PCI Express, the following changeis recommended for the GTX port called DFEDLYOVRD. This value isbased on the most recent characterization results and were not incorporated into the latest legacy TRN interface version of the wrapper. The legacy TRN interface is the 1.# version series of the wrapper. These settings are included in the v2.4 AXI4-Steam interface version of the wrapper.

Note, that if an older version of the core is being used, either an earlier v1.# core or v2.# core, the most recent attributes are available in the v2.4 wrapper with the only difference between v1.7 and v2.4 being the below.

Solution

In the gtx_wrapper_v6.v[hd] file in the core's generated source director, change the port called DFEDLYOVRD to be tied '0' instead of '1'. The old value is not wrong, but this value will allow for more margin and uses the recommended value for DFE clock delay adjustment based on the Virtex-6 FPGA GTX TransceiversUser Guide (UG366).

For asynchronous clocked links, see (Xilinx Answer 42346) for an alternate PMA_RX_CFG value.

Revision History
08/11/2011 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40446 Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues N/A N/A
AR# 43581
Date Created 08/11/2011
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )