We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43586

MIG Spartan-6 MCB - Controller Architecture Design


The Memory Controller Block (MCB) is responsible for receiving all requests from the User Interface and storing them in a logical queue. In processing these requests, the MCB ensures that all functional and timing requirements of the JEDEC standard/memory device are met. The MCBmust ensure that all required commands to complete Reads/Writes are sent (Refresh, Activate, Precharge). This section of the Spartan-6 FPGA Design Assistant focuses on the architecture design of the MCB. Please select from the optionsbelowfor information related to your specific question.

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


For information on each of these blocks, see:

The Memory Controller is discussed in detail in the Spartan-6 FPGAMemory Controller User Guide(UG388). Go to the "MCB Functional Description" > "Architecture Overview".

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43659 MIG Spartan-6 MCB - Controller N/A N/A
43587 MIG Spartan-6 MCB - Datapath N/A N/A
43589 MIG Spartan-6 MCB - Bank Management N/A N/A
43588 MIG Spartan-6 MCB - Arbiter N/A N/A
AR# 43586
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • MIG
Page Bookmarked