The Memory Controller Block (MCB) is responsible for receiving all requests from the User Interface and storing them in a logical queue. In processing these requests, the MCB ensures that all functional and timing requirements of the JEDEC standard/memory device are met. The MCBmust ensure that all required commands to complete Reads/Writes are sent (Refresh, Activate, Precharge). This section of the Spartan-6 FPGA Design Assistant focuses on the architecture design of the MCB. Please select from the optionsbelowfor information related to your specific question.
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The Memory Controller is discussed in detail in the Spartan-6 FPGAMemory Controller User Guide(UG388). Go to the "MCB Functional Description" > "Architecture Overview".