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The AXI Read and Write data width can be 32, 64, or 128. It must be equal to the MCB data width. The MCB data width can be 32, 64, or 128 bits, depending on the MCB configuration.
Each AXI4 slave interface can run with a completely independent clock from each other and from the memory clock. All AXI channels and interface logic within a specific AXI4 slave interface use the same clock, with no additional clock conversion before passing into the associated MCB port.
The address width must be parameterized to support the desired system address bus width. If the system address bus is defined wider than the memory size, it is acceptable to alias/wrap the memory across the address space. The MCB interface supports a maximum of 30 bits for the address bus. The MSB of the AXI address is cut off, if necessary. A 32-bit constant address width is used for compatibility with EDK. The address also wraps if the address range specified by the base and high address is smaller than the memory size.
Read-Only or Write-Only AXI Ports
Each AXI4 interface can be configured as Read-only or Write-only even when connected to a bidirectional MCB port. This permits logic optimization when bidirectional data flow is not required. The Read-only or Write-only AXI port is required when connected to a unidirectional MCB port. When placed in Read-only or Write-only mode, unnecessary Read/Write arbitration logic and datapath logic are removed. If the MCB port is natively a bidirectional port, the MIG GUI and source RTL allow you to choose a Read-only or Write-only AXI4 interface for FPGA resource savings.
The AXI4 interface has a single synchronous reset, active low signaling, that resets the entire core and brings it to a known initialized state. A reset event causes a full reset including recalibration of the controller.
The following burst rules apply:
The following cache bit rules apply:
The AXI Spartan-6 FPGA DDRx Memory Controller ignores the AXI PROT bits and assume all transactions are normal, non-secure accesses.
This IP does not currently support exclusive access.
The AXI Spartan-6 FPGA DDRx Memory Controller always generates an OKAY response.
IDs, Threads, and Reordering
The MCB interface is strictly linear; therefore, no reordering or threads is implemented in the bridge. Transactions are returned in the exact order they are received.
Read/Write Acceptance Depth
The read acceptance depth is five outstanding transactions. The write acceptance depth is four outstanding transactions.
AXI has separate read and write channels. An external memory has only a single address bus. Therefore, the AXI Spartan-6 FPGA DDRx Memory Controller must arbitrate between coincident Read and Write requests to determine which one to execute to memory. The arbitration algorithm for Read and Write requests is Round-Robin.
The AXI Spartan-6 FPGA DDRx Memory Controller is little-endian only.
The AXI Spartan-6 FPGA DDRx Memory Controller does not have to make use of REGION bits and can ignore this signal.
Low Power Interface
The AXI Spartan-6 FPGA DDRx Memory Controller does not support alow power interface.
The AXI Spartan-6 FPGA DDRx Memory Controller does not support QoS.
For more information regarding the AXI interface, please see the Spartan-6 FPGA Memory Interface Solutions User Guide (UG416), in particular, the EDK Flow Details > AXI Spartan-6 FPGA DDRx Memory Controller section.