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AR# 43594

MIG Spartan-6 MCB - JEDEC Specification - Additive Latency

Description

This section of the MIG Design Assistant focuses on the Additive Latency, defined by the JEDEC Specification, as it applies to MIG Spartan-6 MCB designs.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Additive latency is an efficiency feature in SDRAM memories.It is discussed in section 3.4.3.4 of JEDEC Specification JESD79-3 DDR3 SDRAM Standard and 2.5 of JEDEC Specification JESD79-2 DDR2 SDRAM Standard (in the "Bank activate command" section).Additive latency allows a read or write command to be issued immediately following the active command.

This feature is not supported in the MIG Spartan-6 MCB controller and PHY.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40685 MIG Spartan-6 MCB - JEDEC Specification N/A N/A
AR# 43594
Date Created 08/22/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
IP
  • MIG