In the same document, page118, it is explained as, "For the RAW mode, DFE_TRAIN_CTRL_LANEx[15:13]=010, the DFE train limit is ignored in this mode."
What is correct about the DFE train limit?
In the RAW mode. the DFE train limit value is ignored. Customers are not required to set it to any specific value.
Related to this, the following changes will be made in next release of UG371.
": Raw mode train_ok qualifier for the DFE. This bit qualifies the DFETRAINCTRL signal for RAW Mode. This bit defaults to 1'b1 for modes that do not use 8B/10B or 64B/66B encoding or PRBS"
[12:0]: DFE train limit. The reference to Raw will be removed. Customers should ignore this note.
"When DFE_TRAIN_CTRL_LANE is set to 1'b1, asserting DFETRAINCTRL transitions the DFE from training mode to track mode. This is meant to be used in Raw Mode."
"DFETRAINCTRL should be asserted once it is determined that the DFE has trained. In applications where the data is scrambled (pre-scrambling with a LFSR before 8B/10B encoding, 64B66B or 64B67B or 128B/130B encoding), DFETRAINCTRL does not necessarily need to be asserted. In applications where the data is 8B/10B encoded or the encoding is known to be not pseudo-random and a training sequence is available for the DFE to train on, in order to determine that the DFE has trained, at least 10 million UI of correct data should be received before the DFETRAINCTRL is asserted by the user logic. The DFE training sequence is assumed to have rich spectral content similar to PRBS-11 or 64B/66B, 64B/67B, 128B/130B encoding or have a repetition interval of 2000 bits or longer.