Calibrated Input Termination provides on-chip, precisely calibrated termination for DDR2 and DDR3 memory interfacesresulting in superior signal integrity and reduced component count compared to the other available termination options.
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MIG can provide calibrated on-chip input termination for DDR2 and DDR3 memory interfaces. When this option is selectedin the FPGA Option screen of the MIG GUI,it sets the parameterCX_SKIP_IN_TERM_CAL=0 for the top-level MIG generated design which enables the inputtermination calibration algorithm inthe mcb_soft_calibration.v/.vhdmodule. Input Termination Calibration isimplemented through the IODRP2_MCB block(only available through the MIG MCB design)andmatches the internal input impedance of the bidirectional memory interface signals DQ, LDQS_p/n, UDQS_p/n, to an external resistor that is to be connected on the board between the RZQ pin and ground. Because the calibrated inputtermination is implemented through the soft calibration logic, the property IN_TERM=NONE is applied to the bidirectional memory interface signals in the MIG generated UCF.
The soft calibration module uses two I/O pins (RZQ and ZIO) generated by the MIG tool (or EDK) to perform calibration of the input termination. RZQ is a required pin for all MCB designs. When Calibrated Input Termination is used, a resistor must be connected between the RZQ pin and ground with a value that is twice (2R) that of the desired input impedance (e.g., a 100 Ohm resistor to achieve a 50 Ohm effective input termination to Vtt).
The internal termination circuit is created at each dq and dqs pin with an equivalent resistance 2R fromthe I/O to VCCO, and another equivalent resistance 2R from the I/O to ground, effectively creating a Thevenin Equivalent circuit ofR to Vtt (VCCO/2). This internal termination is present whenever the dq and dqs pins are 3-stated, and is disabled when they are driving.
The RZQ pinshould be left as a no-connect (NC) pin for designs not using Calibrated Input Termination. In addition, both the RZQ pin and ZIO pin must be placedwithin the same I/O bank as the memory interface pins.
The ZIO pin is only required for designs using Calibrated Input Termination and must be a no-connect pin (i.e., not connected to any PCB trace) assigned to a valid package pin (i.e., bonded I/O) location within the MCB bank. The default locations of the RZQ and ZIO pins can be found in the UCF constraints files.
For further details onCalibrated Input Termination, seethe"MCB Operation > Calibration > Phase 1: Input Termination" section inthe Spartan-6 FPGA Memory Controller User Guide (UG388): http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
See also: (Xilinx Answer 34055) MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?