UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43638

MIG Spartan-6 MCB - Calibrated Input Termination

Description

Calibrated Input Termination provides on-chip, precisely calibrated termination for DDR2 and DDR3 memory interfacesresulting in superior signal integrity and reduced component count compared to the other available termination options.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

MIG can provide calibrated on-chip input termination for DDR2 and DDR3 memory interfaces. When this option is selectedin the FPGA Option screen of the MIG GUI,it sets the parameterCX_SKIP_IN_TERM_CAL=0 for the top-level MIG generated design which enables the inputtermination calibration algorithm inthe mcb_soft_calibration.v/.vhdmodule. Input Termination Calibration isimplemented through the IODRP2_MCB block(only available through the MIG MCB design)andmatches the internal input impedance of the bidirectional memory interface signals DQ, LDQS_p/n, UDQS_p/n, to an external resistor that is to be connected on the board between the RZQ pin and ground. Because the calibrated inputtermination is implemented through the soft calibration logic, the property IN_TERM=NONE is applied to the bidirectional memory interface signals in the MIG generated UCF.

The soft calibration module uses two I/O pins (RZQ and ZIO) generated by the MIG tool (or EDK) to perform calibration of the input termination. RZQ is a required pin for all MCB designs. When Calibrated Input Termination is used, a resistor must be connected between the RZQ pin and ground with a value that is twice (2R) that of the desired input impedance (e.g., a 100 Ohm resistor to achieve a 50 Ohm effective input termination to Vtt).

IN_TERM_RZQ_ZIO.JPG
IN_TERM_RZQ_ZIO.JPG


The internal termination circuit is created at each dq and dqs pin with an equivalent resistance 2R fromthe I/O to VCCO, and another equivalent resistance 2R from the I/O to ground, effectively creating a Thevenin Equivalent circuit ofR to Vtt (VCCO/2). This internal termination is present whenever the dq and dqs pins are 3-stated, and is disabled when they are driving.

IN_TERM_DQ.JPG
IN_TERM_DQ.JPG

To further increase the noise margin on the DQS pinsfor READ operations, after the 2R value iscalibrated to by soft-calibration logic and applied to all of the DQ pins, a non-symmetrical termination factoris then appliedto eachside (n and p) of each DQSpin (UDQS and LDQS). For the P sides of the DQS pairs, the pull-upconductivity is weakened by applying a factor7/8 (making the pull-up resistance slightly higher at 2R*(8/7)), and the pull-downconductivity is strengthened by applying a factor of 9/8 (making the pull-down resistance slightly lower at 2R*(8/9)). For the N sides of the DQS pairs, the opposite is done. This will have the effect ofpulling the L/UDQS_p a little more towards ground, and L/UDQS_n a little more towards Vcco when the termination is present (during 3-state and READ bursts).

IN_TERM_DQS2.JPG
IN_TERM_DQS2.JPG


The RZQ pinshould be left as a no-connect (NC) pin for designs not using Calibrated Input Termination. In addition, both the RZQ pin and ZIO pin must be placedwithin the same I/O bank as the memory interface pins.

The ZIO pin is only required for designs using Calibrated Input Termination and must be a no-connect pin (i.e., not connected to any PCB trace) assigned to a valid package pin (i.e., bonded I/O) location within the MCB bank. The default locations of the RZQ and ZIO pins can be found in the UCF constraints files.

For further details onCalibrated Input Termination, seethe"MCB Operation > Calibration > Phase 1: Input Termination" section inthe Spartan-6 FPGA Memory Controller User Guide (UG388): http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

See also: (Xilinx Answer 34055) MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43662 MIG Spartan-6 MCB - Soft Calibration N/A N/A
AR# 43638
Date Created 08/24/2011
Last Updated 02/04/2013
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
IP
  • MIG