In the current build of the FPGA, codes 00, 01, and 11 can be used for the Si5324_clkin_sel input port.
Code 00 connects the 27 MHz XO to the Si5324.
Code 01 also connects the 27 MHz XO to the Si5324.
Code 11 connects the external video sync signal to the clock input of the Si5324.
This mode has been used to implement genlock for Spartan-6 SDI demos (see XAPP1076).
Code 10 is not a valid code for use with the Si5324_clkin_sel input port on this mezzanine card.
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