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AR# 43655 Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device

Description

On the Virtex-6 FPGA Broadcast Connectivity Kit FPGA Broadcast Mezzanine Card, the Si5324 device primarily provides a reference clock to the serial transceivers on the carrier board. What codes are used on Si5324_clkin_sel to select the Si5324 clock input source?

Solution


In the current build of the FPGA, codes 00, 01, and 11 can be used for the Si5324_clkin_sel input port.



Code 00 connects the 27 MHz XO to the Si5324.

Code 01 also connects the 27 MHz XO to the Si5324.

Code 11 connects the external video sync signal to the clock input of the Si5324. This mode has been used to implement genlock for Spartan-6 SDI demos (see XAPP1076).

Code 10 is not a valid code for use with the Si5324_clkin_sel input port on this mezzanine card.

Actions

AR# 43655
Date Created 08/17/2011
Last Updated 02/23/2012
Status Active
Type
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