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To create the desired system clock frequency on the I/O clock network, an external clock source drives one of the PLLs in the center column of the device. The external clock frequency is not critical as long as the PLL can synthesize the desired MCB system clocks from it. In general, the preferred PLL location is the one nearest the center of the device that minimizes the physical distance between the PLL and the BUFPLL_MCB block. This PLL location is strongly recommended for larger devices with six PLLs.
The PLL generates two system clock outputs, sysclk_2x and sysclk_2x_180, that are twice the frequency of the desired memory clock (for example, for a 667 Mb/s DDR2 interface with a memory clock equal to 333 MHz, the system clocks are set to 667 MHz) and 180 degrees out of phase from each other. Only two clock lines are available on each side of the device to drive the I/O clock network from the PLLs. The pair of system clocks uses these two clock lines to connect to the MCBs on the left or right side of the device. Thus for devices with four MCBs, the two MCBs on the same side of the device must share the same system clock pair and therefore must run at the same data rate, although the memory standard implemented can be different. DCMs do not have access to the I/O clock network and cannot, therefore, be used to drive MCBs. It is also possible to drive MCBs on both sides of the device from a single PLL. In this case, two BUFPLL_MCB blocks (one on each side of the device) must be driven by the shared PLL.
When the pair of system clocks reaches the I/O clock network, they are rebuffered by a BUFPLL_MCB driver. This driver also creates clock enable strobes required by the MCB: pll_ce_0 and pll_ce_90. The attributes of the BUFPLL_MCB primitive should be set as follows to create the necessary clock enable strobe behavior for the MCBs:
LOCK_SRC = "LOCK_TO_0"
DIVIDE = 2
The rebuffered full rate system clocks (2X clocks) are used in the PHY layer of the interface to create the necessary double data rate (DDR) signaling at the I/O pins (for example, a 667 MHz clock is used to generate an effective 667 Mb/s DDR signal at the I/O). A divide-by-two circuit in the MCB creates what is traditionally considered the memory clock frequency (for example, 333 MHz for a 667 Mb/s DDR interface). These 1X clocks drive the controller, arbiter, and other single data rate (SDR) logic.
The calibration related clock, mcb_drp_clk, must be generated by the PLL and must be phase-synchronized (i.e., in phase) with the sysclk_2x domain. The calibration clock rate is limited by normal static timing analysis, with a typical achievable frequency of 100 MHz. In general, a calibration clock frequency of at least 50 MHz should be used to allow the MCB to complete calibration operations in a reasonable period of time.
A set of user clocks is associated with each of the User Interface ports (port number X = 0 to 5) used in a given design, as follows:
pX_cmd_clk: Command FIFO user clock for clocking in the Address, Instruction, and Burst Length from the FPGA logic into the FIFO.
pX_wr_clk: Write Data FIFO user clock for loading write data from the FPGA logic into the FIFO in preparation for a burst to memory.
pX_rd_clk: Read Data FIFO user clock for clocking out data returning from the memory into the FPGA logic.
The user clocks are completely asynchronous from the system and calibration clocks and therefore they can operate at any frequency dictated by the FPGA logic portion of the design. The FIFOs inside the MCB handle the necessary clock domain transfer. For best utilization of the available memory bandwidth, the user clocks should be set at or above the frequency determined by the ratio of the User Interface to the external Memory Device interface. For example:
For a DDR3 800 Mb/s interface with the memory clock = 400 MHz and a x8 bit memory device:
The result is 16 bits of data transfer per clock cycle (8 bits on each clock edge)
For a x64 bit User interface:
The user clock should be set at or above (16/64) * 400 MHz = 100 MHz
While not technically required, it is also highly recommended that all three user clocks for a port (pX_cmd_clk, pX_wr_clk, and pX_rd_clk) be driven by the same clock source from the FPGA logic to avoid complex timing and synchronization issues in the user design.