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AR# 43706

AXI Bridge for PCI Express - How to connect the axi_aclk and axi_ctl_aclk Ports

Description

The ports tab of the System Assembly View shows the axi_aclk and axi_ctl_aclk as inputs to the three AXI interconnect ports. What clocks should drive these input clocks?

Solution

The axi_aclk and axi_ctl_aclkports should be connected to the axi_aclk_out and axi_ctl_aclk_out clocks, respectively. This will prevent any transferring of clock domains within the core.

Release History
11/28/2011 - Title update
08/19/2011 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44972 AXI Bridge for PCI Express FAQ N/A N/A
AR# 43706
Date Created 08/18/2011
Last Updated 01/23/2013
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)