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AR# 43717 System Generator for DSP 13.x - Why do I get a block RAM compilation error - HDLCompiler:1156?

Description


When designing with block RAM in System Generator for DSP 13.x, the following error is occurring:



ERROR:HDLCompiler:1156 - "D:\Proyectos\Mercury2M\MercuryMax_v1.0_5291_ISE132\hdl\FrameBuffer\SEN2APP\ngc_netlist\top_level_0_SEN2APP_Ram2App\synth_?model\ram2app.vhd" Line 4215: Formal port <ena> does not exist in entity <bmg_62_32b795b05d9d5932>. Please compare the definition of block <bmg_62_32b795b05d9d5932> to its component declaration and its instantion to detect the mismatch.
INFO:HDLCompiler:1408 - "D:\Proyectos\Mercury2M\MercuryMax_v1.0_5291_ISE132\hdl\FrameBuffer\SEN2APP\ngc_netlist\top_level_0_SEN2APP_Ram2App\synth_model\ram2app.vhd" Line 306. bmg_62_32b795b05d9d5932 is declared here
ERROR:HDLCompiler:1156 - "D:\Proyectos\Mercury2M\MercuryMax_v1.0_5291_ISE132\hdl\FrameBuffer\SEN2APP\ngc_netlist\top_level_0_SEN2APP_Ram2App\synth_model\ram2app.vhd" Line 4216: Formal port <enb> does not exist in entity <bmg_62_32b795b05d9d5932>. Please compare the definition of block <bmg_62_32b795b05d9d5932> to its component declaration and its instantion to detect the mismatch.



What is the workaround for this issue?

Solution


This is a known issue. There are two workarounds:
  • Create the HDL Netlist in Sysgen and then modify the HDL to remove the ena and enb ports from the VHDL files.
    Then, run the remaining design through Project Navigator to implement the design. This was used to work around the problem in a previous customers design.
  • Create the Block Memory Core through CORE Generator and incorporate the resulting core as a black box in your System Generator design.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Actions

AR# 43717
Date Created 01/16/2012
Last Updated 01/16/2012
Status Active
Type
Tools
  • System Generator for DSP - 13.1
  • System Generator for DSP - 13.2
  • System Generator for DSP - 13.3
  • System Generator for DSP - 13.4
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