We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43718

How to meet PCIe configuration timing


Customer is running into an issue with configuration timing due to a 100 ms requirement on PCI Express for an active link once power is stable.


For the V6 solution refer to XAPP883 http://www.xilinx.com/support/documentation/application_notes/xapp883_Fast_Config_PCIe.pdf

The designer would create a partial reconfiguration project to activate the link within the time requirement as the rest of the design is being loaded.

For S6, refer to http://www.xilinx.com/support/documentation/user_guides/s6_pcie_ug654.pdf
Table 8-2: Configuration Time Matrix (ATX Motherboards): Spartan-6 FPGA
of UG654 for programming times. The CCLK frequency requirements are met by using USERCCLK to provide the input clock as this speed is higher than can be met by the internal oscillator.

For the 7 Series solution we have the Tandem PROM and Tandem PCIe.

Tandem PROM will be enabled in SW via an IP patch to select Beta customers. First stage loads up the PCIe portion of the design and then second stage loads up the remainder of the User design. Bitstream is loaded via external PROM.

Tandem PCIe will be tentatively be available to Beta customers beginning in 14.1. First stage will load from external PROM and boot up the PCIe portion. Remainder of the bitstream will be loaded via PCIe.
AR# 43718
Date Created 08/18/2011
Last Updated 05/23/2013
Status Archive
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less