We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43729

ISE13.2: Global signal defined in VHDL package causes XST errors


My design uses a global signal defined in a VHDL package to make it available for easier access from multiple hierarchical levels.

This causes the following XST error:

ERROR:Xst:2548 - " " line xx: Signal 'xxxx' defined in a package is already used in entity .


Although this kind of usage is technically legal in VHDL, it is typically considered poor design practice to use global signals in this manner.

The work-around is to pass all signals through port interfaces.
AR# 43729
Date Created 08/19/2011
Last Updated 03/05/2015
Status Active
Type General Article
  • FPGA Device Families