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AR# 43876

MIG 7 Series DDR3/DDR2 - Generating Reference Clock from Existing PLL Resource


The 7 series DDR3/DDR2 MIG design has two clock inputs, the reference clock and the system clock input.

The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks (used in the user interface, controller, and PHY layers) and drives the PLL instantiated in the infrastructure module.

The reference clock can be generated from the existing PLL resource instead of driving it from an external clock source.


To generate the reference clock internally from a single clock source, the following two options are available:

  1. When generating MIG IP, select the Use System Clock option for the Reference Clock:


Note: The "Use System Clock" option is only available when an Input Clock Period of "5000 ps (200 MHz)" is chosen.

 2. Manually internally generate the Reference Clock:

  • When generating the MIG IP select the No Buffer option for the Reference Clock:


  • The RTL files that need to be changed are example_top.v/.vhd, <user_design>.v/.vhd, and infrastructure.v and iodelayctrl.v.
  • To find out the settings of PLL, invoke the Clocking Wizard from the CORE Generator interface and provide the source clock frequency.
    Also, configure the Clocking Wizard to generate five outputs: four outputs required for the default design of MIG, and the fifth output as the idelayctrl reference clock (200 MHz).
    Make a note of the generated multiplication factor (CLKFBOUT_MULT_F), divide factor (DIVCLK_DIVIDE), and respective clock output divide factor (CLOCKn_DIVIDE).
  • Module infrastructure changes:
    1. An additional new parameter should be added for the fifth clock output which would take the value of CLOCK5_DIVIDE; name this parameter as CLKOUT5_DIVIDE.
      Also, pass this parameter to the CLKOUT5_DIVIDE parameter of the PLLE2_ADV instance (or) the CLKOUT5_DIVIDE parameter value can be directly mapped to CLKOUT5_DIVIDE parameter of PLLE2_ADV instance in the infrastructure module.
    2. In the "infrastructure.v" file, add an additional output port as clk_ref, which is a 200 MHz clock generated from the PLL.
      This should be connected to CLKOUT5 port of PLL.
      This clock drives the iodelayctrl module.
  • MIG Design Top Module changes (example_top.v/vhd or user design top):
    • Replace the parameter values of CLKFBOUT_MULT, DIVCLK_DIVIDE, and CLKOUT#_DIVIDE with the newly generated factors.
      Please note that CLKOUT#_DIVIDE parameters should have the values of each CLOCK#_DIVIDE generated by the Clocking Wizard.
  • UCF Changes:
    • The idelayctrl reference clock is generated from the PLL, there is no need to provide idelayctrl clock constraints in UCF.
      Therefore, comment out the idelayctrl reference clock constraints in UCF.
AR# 43876
Date Created 09/19/2011
Last Updated 12/19/2014
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
  • MIG 7 Series