This answer record provides a downloadable MIG 7 Series DDR3/DDR2 Hardware Debug Guide in PDF format to enhance its usability. Answer records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.
Note: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Please download the 7 Series MIG DDR3/DDR2 Hardware Debug Guide (PDF) attached to the end of this solution.
This document describes techniques to debug calibration failures and data errors related to designs using the 7 series MIG DDR3 SDRAM core. A complete list of signals to capture in the ChipScope Pro tool when debugging calibration failures and data errors has been provided. ChipScope Pro tool screen captures illustrate how to analyze those signals and establish theories on potential root causes.
Please use the 7 Series Calibration Results spreadsheet (ar43879_7series_ddr3_cal_results.xlsx), attached to the end of this solution, to capture the results.
Revision History:
10/12/2012 - Updated attachments
10/05/2012 - Added PRBS Read Leveling, Traffic Generator Data Error Debug, and Window Margin Check
07/19/2012 - Added content to Data Error Debug sections.
06/04/2012 - Updated CK to DQS Trace Matching Guidelines and added content to Isolating Data Errors section.
05/08/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46227 | MIG 7 Series Solution Center - Top Issues | N/A | N/A |
| 51315 | Xilinx MIG 7 Series Solution Center Design Assistant - Hardware usage and debug | N/A | N/A |
| 35094 | MIG Virtex-6 and 7 Series DDR3 - Write Leveling | N/A | N/A |
| 34923 | MIG Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Design Signal and Parameter Descriptions | N/A | N/A |
| 51914 | MIG 7 Series DDR3/DDR2 - Generated RTL Parameter, UCF Constraint, and Signal Descriptions | N/A | N/A |
| 51954 | MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration | N/A | N/A |
| 34359 | MIG Virtex-6 and 7 Series DDR3 - Jedec Specification - Multi-Purpose Register | N/A | N/A |
| 52808 | KC705 Example Designs - MIG Design Files enhanced window margining | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51667 | Xilinx MIG 7 Series Solution Center - Design Assistant - Simulation Debug | N/A | N/A |