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AR# 43894

13.2 ChipScope - Virtex-6 GTX IBERT "ERROR:Place:1145 Unroutable placement error when generating the core..."


If I generate a Virtex-6 GTX IBERT design using 13.2, the following error occurs when using more than 7 GTX transcievers in the IBERT core:

"ERROR:Place:1145 - Unroutable Placement! A GT / BUFGCTRL clock component pair have been found that are not placed at a routable GT / BUFGCTRL site pair. The GT component <U_CHIPSCOPE_IBERT3/U0/U_IBERT_CORE/U_GTCPX_X0Y14/U_GT/gtxe1_i> is placed at site <GTXE1_X0Y14>. The corresponding BUFGCTRL component <U_CHIPSCOPE_IBERT3/U0/U_IBERT_CORE/U_GTCPX_X0Y14/U_RXRECCLK_BUFG> is placed at site <BUFGCTRL_X0Y11>. The pair can use the fast path between the GT and the Clock buffer if the GT and BUFGCTRL are both placed in the same half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used inFPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING. < PIN "U_CHIPSCOPE_IBERT3/U0/U_IBERT_CORE/U_GTCPX_X0Y14/U_GT/gtxe1_i.RXRECCLK" CLOCK_DEDICATED_ROUTE = FALSE; >"


This is a known issue in 13.2 for the Virtex-6 GTX IBERT core that is scheduled to be fixed in 13.3.

If you experience this error, please open a WebCase with Xilinx Technical Support using the following link:

Xilinx Technical Support will provide further assistance on using WebCase.

AR# 43894
Date Created 08/31/2011
Last Updated 01/02/2013
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
  • ChipScope Pro - 13.2