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AR# 43949

7 Series Integrated Block for PCI Express - Link Training Fails due to Incorrect MGT Attributes Using Core v1.1 rev 1


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

This patch should only be applied to ISE 13.2 software. Once ISE 13.3 is released with v1.2 of the core, update to ISE 13.3 and use v1.2. The changes in this patch are included in ISE 13.3 v1.2 core.

When using v1.1 Rev 1 of the 7 Series Integrated Block wrapper on Initial Engineering Sample (ES) silicon (CES9937), the block will not link up. This patch includes new MGT attributes that will enable the block to link train.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


This patch creates a v1.1 Rev 2 installation of the 7 Series Integrated Block for PCI Express. Download the patch from here:


The patch_readme folder includes a readme file withmore information about the patch.

See (Xilinx Answer 40469) for other known issues related to the 7 Series Integrated Block for PCI Express.

For other Kintex-7 engineering sample known issues, see (Xilinx Answer 43347).
Forother Virtex-7 engineering sample known issues, see (Xilinx Answer 43423).

There are two ways to install this patch:

Option 1: Overwrite the existing installation

Install the Patch by extracting the contents of the ".zip" archive to the root directory of the XILINX (Xilinx ISE installation). This patch includes the core's installation path starting with the "coregen" directory. For example, unzip to:


Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

IMPORTANT: If the extractor does not ask to overwrite existing files, then you are not targeting the correct path when extracting the files.

Option 2: Use the MXILINX environment variable

Extract these files to any directory and set the MYXILINX variable to point to that directory. When the CORE Generator is launched, the existence of the MYXILINX variable instructs the software to override the existing core with the one pointed to by MYXILINX.

For further information on finding the Xilinx installation and using the environmentvariable, see (Xilinx Answer 11630).
For further information on using the MYXILINX environment variable, see (Xilinx Answer 2493).

NOTE: You might be required to have system administrator privileges to install the patch if you do not have write permissions to the Xilinx installation directory, or cannot use the MYXILINX option.

Revision History
12/06/2011 - Added version resolved reference to AR 40469
10/27/2011 - Added information about ISE 13.3 and v1.2
09/26/2011 - Added reference to 43347 and 43423.
09/08/2011 - Initial Release

AR# 43949
Date Created 09/08/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
  • Kintex-7
  • AccelDSP - 13.2