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AR# 43954

Virtex 6-WARNING:Route:436 - The router has detected an unroutable situation for one or more connections.

Description

I have received the following warning in PAR.

It states that the clock net (sys_clk_c) cannot be routed to the rest of the logic in the fabric:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the

design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.

To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:

Unroutable signal: sys_clk_c pin:

EP/tx_fifo0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1]

.ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram/CLKARDCLKL

Unroutable signal: sys_clk_c pin:

EP/tx_fifo0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1]

.ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram/CLKARDCLKU

Unroutable signal: sys_clk_c pin:

EP/tx_fifo0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0]

.ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram/CLKARDCLKL

Unroutable signal: sys_clk_c pin:

EP/tx_fifo0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0]

.ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram/CLKARDCLKU

Unroutable signal: sys_clk_c pin:

EP/RX_FIFO0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1]

.ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram/CLKBWRCLKL


How can the unroutability issue be resolved in this scenario?

Solution

The sys_clk_c in this scenario is an output of differential IBUFDS.

It is not driven by a BUFG where the output of IBUFDS is connected to different logics in the FPGA Fabric.

As a result, the tool is trying to use the local routing resources to route between the logic in the fabric.

This results in the design is being unrouted.


Inserting a BUFG after the output of IBUFDS allows the tool to use the global routing resources and the design is routed completely.

AR# 43954
Date Created 09/06/2011
Last Updated 03/23/2015
Status Active
Type General Article
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 13.2