UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44011

7 Series Integrated Wrapper for LogiCORE CPRI - IBUFDS_GTE2 Use Model Change

Description

An IBUFDS_GTE2 primitive drives the GTX reference clocks and there are two IBUFDS_GTE2 elements per Quad as shown in Figure 2-4 of the7 Series FPGAs GTX Transceivers User Guide (UG476), driving GTREFCLK0 and GTREFCLK1. The common use mode is to instantiate one IBUFDS_GTE2 and drive one of the two reference clocks.

There is a software issuethat causes the swing of the reference clock going into the Quad to be set incorrectly when only one IBUFDS_GTE2 primitive is instantiated in a Quad.As a result, you need to update your instantiations to account for these port changes.

For more information, please see (Xilinx Answer 43339)as well.

Solution

This article describes an issue in version 13.2 of the software tools where the voltage swing of the reference clock is set incorrectly when only one IBUFDS_GTE2 in a quad is instantiated.

To work around this problem:

  1. Instantiate the second IBUDFDS_GTE2 in the quad.
  2. Add the following code to the top level example design:

    refclk1_ibufds : IBUFDS_GTE2
    port map (
    I => refclk1_p,
    IB => refclk1_n,
    => refclk1,
    CEB => '0',
    ODIV2 => open );

The refclk1_p and refclk1_n pins are input ports in the top-level design. Place these as the inputs to the unused IBUFDS_GTE2 in the quad.

For example, in the XC7K325T, the transceivers GTXE2_CHANNEL_X0Y8 through GTXE2_CHANNEL_X0Y11 occupy the quad with reference clock inputs at G8, G7 (GTREFCLK0) and J8, and J7 (GTREFCLK1). If the reference clock (refclk_p and refclk_n in the example design) is input on pins G8 and G7, then place refclk1_p and refclk1_n in locations J8 and J7.

Route the output of the new IBUFDS_GTE2 (refclk1 in the above code) through the block level and transceiver wrappers to the GTREFCLK1 port of the GTXE2_CHANNEL component.

If the reference clock is input on pins J8 and J7, then place refclk1_p and refclk1_n at G8 and G7, respectively. Route the refclk1 output through the transceiver wrappers to port GTREFCLK0 of the GTXE2_CHANNEL. Set the CPLLREFCLKSEL port to "010" to select GTREFCLK1 as the clock input of the transceiver.

For more information, see the LogiCORE CPRI Release Notes and Known Issues (Xilinx Answer 36969).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A

Associated Answer Records

AR# 44011
Date Created 10/05/2011
Last Updated 05/22/2012
Status Archive
Type Known Issues
Tools
  • ISE Design Suite - 13.2
IP
  • CPRI