UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44088

13.3 EDK, AXI_V6_DDRx - External Memory Model Simulations Fail when Using ECC

Description

When using the AXI_V6_DDRx core in ECC with the XPS-generated testbench, the memory does not complete calibration, as indicated by phy_init_done. How do I resolve this issue?

Solution

This issue is caused by the uninitialized memory model returning X's during calibration. A possible workaround to this issue is to add the wire delay (wiredly.v) to the testbench, generated from a standalone CORE Generator MIG core generation. This module converts the 'X' signal to a valid logic value that the calibration logic can calibrate to.
AR# 44088
Date Created 09/13/2011
Last Updated 10/25/2011
Status Active
Type Known Issues
Devices
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • EDK - 13.3