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AR# 44088

13.3 EDK, AXI_V6_DDRx - External Memory Model Simulations Fail when Using ECC


When using the AXI_V6_DDRx core in ECC with the XPS-generated testbench, the memory does not complete calibration, as indicated by phy_init_done. How do I resolve this issue?


This issue is caused by the uninitialized memory model returning X's during calibration. A possible workaround to this issue is to add the wire delay (wiredly.v) to the testbench, generated from a standalone CORE Generator MIG core generation. This module converts the 'X' signal to a valid logic value that the calibration logic can calibrate to.
AR# 44088
Date Created 09/13/2011
Last Updated 10/25/2011
Status Active
Type Known Issues
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • EDK - 13.3