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AR# 4409

SYNPLIFY: How to disable RAM inference using the syn_ramstyle attribute?

Description


General Description: How to disable RAM inference in HDL

using Synplicity's Synplify?



A RAM structure can be modeled as a 2-dimensional array of

registers. Each element of the array is known as a word.

Each word can be one or more bits. Synplify automatically

detects the RTL description of a synchronous RAM. The RAM

is mapped to applicable technology specific RAM cells.



When a RAM block is recognized, Synplify will automatically

implement a single-port circuit using RAM16x1S and a dual-port

circuit using RAM16x1D primitives.



Note: Use Synplify 5.0 or greater.

Solution


Designers can disable the usage of select RAMs to map into

standard logic and registers when more efficient. Set the

attribute syn_ramstyle to "registers".



Place the attribute on the output signal driven by the inferred

RAM. Remember to include the range of the output signal (bus)

as part of the name. For example,



define_attribute {a|dout[3:0]} syn_ramstyle "registers"



In HDL Analyst, the output signal name (in the example,

"a" is the instance name and "dout [3:0]" is the output

signal name) will become the instance name of the RAM.
AR# 4409
Date Created 08/31/2007
Last Updated 05/23/2011
Status Archive
Type General Article