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AR# 44098

MIG Spartan-6 FPGA DDR2/DDR3 - Example Design Usage

Description

The Spartan-6 FPGA MIG DDR2/DDR3 design can be generated with two output designs: the User Design and the Example Design.This section of the MIG Design Assistant focuses on the MIG-generated Example Design.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The MIG-generated Example Design includes a synthesizable test bench to generate various traffic data patterns to the memory controller that are fully verified in the simulation and hardware.This synthesizable test bench is called the Traffic Generator.The example design can be used to observe the behavior of the MIG design both in the simulation and the hardware.It is also a powerful aid in identifying design and board-related problems. Verifying a proper simulation environment and a working board with the example design are recommended starting points in your design flow.

For a complete description on the usage of the Example Design for Spartan-6 DDR3/DDR2 designs, please see the "Getting Started" ->"MIG Example Design with Traffic Generator (CORE Generator Tool Native Interface Only)"section in the Spartan-6 FPGA Memory Interface Solutions User Guide (UG416).

For detailed information on the traffic generation used within the Example Design and how to modify it, please see(Xilinx Answer 44093).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44093 MIG Spartan-6 DDR2/DDR3 - Traffic Generator Details and Usage N/A N/A
44095 MIG Spartan-6 FPGA DDR2/DDR3 - MIG Output N/A N/A
AR# 44098
Date Created 11/14/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG Virtex-6 and Spartan-6